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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 1/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology features general description block diagram ? ieee802.3 and ieee802.3u compliant. ? single chip, low cost, two port switch controller. ? build_in embedded memory on chip for packet buffering. ? provide 2 mii/rmii (reduced media indepen- dent interface) ports. ? a flexible mii interface design can directly con- nect with standard mii or pseudo mii. ? support half/full duplex operation per port. ? optional back_pressure control for half_duplex mode. ? provide ?store and forward? switching, and for- warding rate at full_wire speed. ? support up to 2048 mac addresses filtering database, and automatical address aging_out function (300 secs). ? low power cmos design, with single 3.3v supply voltage, 50 mhz operation. ? provide 128 pin pqfp package (MTD502EF), and 80 pin lqfp package (mtd502eg). 2 port 10m/100m switch with build_in memory the mtd502e is a highly integrated, 10m/ 100m two port switch controller with build_in embedded memory. it supports 2 mii/rmii ports for 10m/100m operation, and both can operate under half or full duplex mode. the mtd502e is an ideal solution for two port bridge or dual speed hub application, and no need any external memory buffers in application design. the flexible mii interface design can directly connect with pseudo mii interface (am79c901, homepna phy). the mtd502e provides packet forward- ing, address filtering, learning, and aging func- tion, and have an optional back_presure control implemented in half duplex mode. the mtd502e supports an effective address filtering database, which can recognize up to 2048 mac addresses. it also support an automatical aging function for address table updating (aging time is 300 secs default). port1 dma two embedded memory mii0 mii1 port0 dma mac0 mac1 port switch engine
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product.e 2/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology system diagram 1). two port switch application (homepna to lan) 2). dual speed hub application 10m/100m mii0 transformer rj45 homepna mii1 transformer rj11 physceiver physceiver mtd502e 10m/100m repeater mtd502e (without 2p_sw) 10m/100m repeater (without 2p_sw) expansion bus .......
3/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 1.0 pin connection (under mii mode) 1) 128 pin pqfp (MTD502EF) 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 n c n c n c n c l n k r x 0 _ l e d l n k r x 1 _ l e d l n k a c t 0 _ l e d l n k a c t 1 _ l e d f d c o l 0 _ l e d f d c o l 1 _ l e d g n d c o l 0 _ l e d c o l 1 _ l e d n c n c n c n c n c n c n c g n d n c n c n c n c n c n c n c g n d n c v c c n c n c n c n c v c c n c n c vcc nc gnd nc nc nc nc nc nc nc nc clk25out nc nc gnd nc nc nc vcc sysclk gnd nc nc nc nc rstb 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 l i n k 0 t x d 0 _ 3 v c c t x d 0 _ 2 n c n c n c n c t x d 0 _ 1 t x d 0 _ 0 t x e n 0 t x c 0 n c g n d r x c 0 n c n c n c r x d 0 _ 0 r x d 0 _ 1 f u l l 0 n c n c n c r x d 0 _ 2 r x d 0 _ 3 r x d v 0 c r s 0 c o l 0 s p e e d 0 v c c g n d l i n k 1 t x d 1 _ 3 t x d 1 _ 2 n c n c n c MTD502EF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 speed1 col1 crs1 rxdv1 gnd vcc rxd1_3 rxd1_2 nc nc nc full1 rxd1_1 rxd1_0 nc nc nc rxc1 gnd vcc nc txc1 txen1 txd1_0 txd1_1 nc
4/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 2) 80 pin lqfp (mtd502eg) 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nc vcc nc gnd nc nc nc nc nc nc nc clk25out vcc sysclk nc rstb link0 txd0_3 vcc txd0_2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 n c t x d 0 _ 1 t x d 0 _ 0 t x e n 0 t x c 0 g n d r x c 0 n c n c n c r x d 0 _ 0 r x d 0 _ 1 f u l l 0 n c r x d 0 _ 2 r x d 0 _ 3 r x d v 0 c r s 0 c o l 0 s p e e d 0 mtd502eg 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 col1 crs1 rxdv1 gnd vcc rxd1_3 rxd1_2 nc full1 rxd1_1 rxd1_0 rxc1 txc1 txen1 txd1_0 txd1_1 nc txd1_2 txd1_3 link1 n c n c l n k r x 0 _ l e d l n k r x 1 _ l e d l n k a c t 0 _ l e d l n k a c t 1 _ l e d f d c o l 0 _ l e d f d c o l 1 _ l e d g n d g n d c o l 0 _ l e d c o l 1 _ l e d g n d g n d g n d g n d v c c v c c s p e e d 1 v c c
5/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 2.0 pin descriptions MTD502EF (128pqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions 1 i link0 (nc) link0 (nc) pin 1~32 for port0, suitable for connecting with 10/ 100phy , risc_cpu, switch,.... 2 o txd0_3 rxd0_3 (nc) (nc) 3 vcc 4 o txd0_2 rxd0_2 (nc) (nc) 5 o (nc) crs0 (nc) (nc) 6~8 i (nc) (nc) (nc) (nc) 9 o txd0_1 rxd0_1 (nc) (nc) 10 o txd0_0 rxd0_0 (nc) (nc) 11 o txen0 rxdv0 (nc) (nc) 12 i txc0 (nc) (nc) (nc) 13 i (nc) (nc) (nc) (nc) 14 gnd 15 i rxc0 (nc) crsdv0 txen0 16 o (nc) rxc0 txd0_1 rxd0_1 17 o (nc) col0 txd0_0 rxd0_0 18 o (nc) txc0 txen0 crsdv0 19 i rxd0_0 txd0_0 rxd0_0 txd0_0 20 i rxd0_1 txd0_1 rxd0_1 txd0_1 21 i full0 full0 full0 (nc) 22~24 o (nc) (nc) (nc) (nc) 25 i rxd0_2 txd0_2 (nc) (nc) 26 i rxd0_3 txd0_3 (nc) (nc) 27 i rxdv0 txen0 (nc) (nc) 28 i crs0 speed0 speed0 (nc) 29 i col0 (nc) (nc) (nc) 30 i speed0 (nc) (nc) (nc) 31 vcc 32 gnd 33 i link1 (nc) link1 (nc) pin 33~64 for port1, suitable for connecting with homepna phy. 34 o txd1_3 (nc) (nc) (nc) 35 o txd1_2 (nc) (nc) (nc) 36 o (nc) (nc) (nc) (nc) 37,38 i (nc) (nc) (nc) (nc) 39 i (nc) (nc) crsdv1 (nc) 40 o txd1_1 (nc) txd1_1 (nc) 41 o txd1_0 (nc) txd1_0 (nc) 42 o txen1 (nc) txen1 (nc) 43 i txc1 (nc) rxd1_0 (nc) 44 i (nc) (nc) rxd1_1 (nc) 45 vcc
6/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 46 gnd 47 i rxc1 (nc) full1 (nc) 48~50 o (nc) (nc) (nc) (nc) 51 i rxd1_0 (nc) (nc) (nc) 52 i rxd1_1 (nc) (nc) (nc) 53 i full1 (nc) speed1 (nc) 54~56 o (nc) (nc) (nc) (nc) 57 i rxd1_2 (nc) (nc) (nc) 58 i rxd1_3 (nc) (nc) (nc) 59 vcc 60 gnd 61 i rxdv1 (nc) (nc) (nc) 62 i crs1 (nc) (nc) (nc) 63 i col1 (nc) (nc) (nc) 64 i speed1 (nc) (nc) (nc) 65~66 i (nc) (nc) (nc) (nc) 67 vcc * 68~71 io (nc) (nc) (nc) (nc) 72 vcc 73 io (nc) (nc) (nc) (nc) 74 gnd 75,76 io (nc) (nc) (nc) (nc) 77~79 i (nc) (nc) (nc) (nc) 80 o (nc) (nc) (nc) (nc) 81 io (nc) (nc) (nc) (nc) 82 gnd 83~85 io (nc) (nc) (nc) (nc) 86~88 i (nc) (nc) (nc) (nc) 89 o (nc) (nc) (nc) (nc) 90 io co1_d co1_d co1_d co1_d port1: col led display, low_active. * when in half duplex mode: this led pin present port1?s collision event. 91 io co0_d co0_d co0_d co0_d port0: col led display, low_active. * when in half duplex mode: this led pin present port0?s collision event. 92 gnd 93 io fdco1_d fdco1_d fdco1_d fdco1_d port1: full/col led display, low_active. * when in full duplex mode: this led pin is always in low_active. when in half duplex mode: this led pin present port1?s collision event, using flash style for display. MTD502EF (128pqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions
7/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 94 io fdco0_d fdco0_d fdco0_d fdco0_d port0: full/col led display, low_active. * when in full duplex mode: this led pin is always in low_active. when in half duplex mode: this led pin present port0?s collision event, using flash style for display. 95 io lnac1_d lnac1_d lnac1_d lnac1_d port1: link_activity led display, low_active. * when in link_on state : this led pin is always in low_active. when have tx or rx activity in this port : this led pin present port1?s tx/rx activity, using flash style for display. 96 io lnac0_d lnac0_d lnac0_d lnac0_d port0: link_activity led display, low_active. * when in link_on state : this led pin is always in low_active. when have tx or rx activity in this port : this led pin present port0?s tx/rx activity, using flash style for display. 97 io lnrx1_d lnrx1_d lnrx1_d lnrx1_d port1: link_rx led display, low_active. * when in link_on state : this led pin is always in low_active. when have rx activity in this port : this led pin present port1?s rx activity, using flash style for dis- play. 98 io lnrx0_d lnrx0_d lnrx0_d lnrx0_d port0: link_rx led display, low_active. * when in link_on state : this led pin is always in low_active. when have rx activity in this port : this led pin present port0?s rx activity, using flash style for dis- play. 99~102 io (nc) (nc) (nc) (nc) 103 vcc 104 io (nc) (nc) (nc) (nc) 105 gnd 106~110 io (nc) (nc) (nc) (nc) 111 io (nc) p0mdio (nc) p0mdio 112 io (nc) p0mdc (nc) p0mdc 113 io (nc) (nc) (nc) (nc) 114 io clk25o clk25o clk25o clk25o clock 25mhz output. 115~116 io (nc) (nc) (nc) (nc) 117 gnd 118~120 io (nc) (nc) (nc) (nc) 121 vcc 122 i sysclk sysclk sysclk sysclk system clock input, 50mhz operation. 123 gnd MTD502EF (128pqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions
8/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology note: input signal link,speed,full from phy device are low_active definnition. 124~127 io (nc) (nc) (nc) (nc) 128 i rstb rstb rstb rstb system resetb input, low_active. MTD502EF(128pqfp) jumper setting table after power on reset pin no. io setting function descriptions 5 io 2p_sw enable jumper setting function after power on reset. -external pull_high = 1, means enter 2 port switch mode. -external pull_low = 0, means an internal test mode. -external floating : default is 0. for mtd502e application, this pin must always use ?external pull_hgih? for well operation. 18 io back pressure disable jumper setting function after power on reset. -external pull_high = 1, means back_pressure function ( under half_duplex) is disabled for two ports both. -external pull_low = 0, means back_pressure function enable. -external floating : default is 0. 95 io p1_rmii enable jumper setting function after power on reset. -external pull_high = 1, means port 1 rmii interface enable.. -external pull_low = 0, means port 1 is mii interface. -external floating : default is 0. 97 io p0_rmii enable jumper setting function after power on reset. -external pull_high = 1, means port 0 rmii interface enable.. -external pull_low = 0, means port 0 is mii interface. -external floating : default is 0. 98 io p0_phy_mode enable jumper setting function after power on reset. -external pull_high = 1, means port 0 interrface enter phy mode. -external pull_low = 0, means port 0 interface is using mac mode. -external floating : default is 0. 100 io p1_bkoff_4 enable jumper setting function after power on reset. -external pull_high = 1, means port 1 mac backoff engine is using limit_4 modified method. -external pull_low = 0, means port 1 mac backoff engine is using specification defined method. -external floating : default is 0. MTD502EF (128pqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions
9/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 101 io p0_bkoff_4 enable jumper setting function after power on reset. -external pull_high = 1, means port 0 mac backoff engine is using limit_4 modified method. -external pull_low = 0, means port 0 mac backoff engine is using specification defined method. -external floating : default is 0. 102 io deviceid[4] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 104 io deviceid[3] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 106 io deviceid[2] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 107 io deviceid[1] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 108 io deviceid[0] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 109 io p1_crcchk disable jumper setting function after power on reset. -external pull_high = 1, means port1 crc check and drop function is disabled. -external pull_low = 0, means port1 crc check and drop function is enabled. -external floating : default is 0. MTD502EF(128pqfp) jumper setting table after power on reset pin no. io setting function descriptions
10/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 110 io p0_crcchk disable jumper setting function after power on reset. -external pull_high = 1, means port0 crc check and drop function is disabled. -external pull_low = 0, means port0 crc check and drop function is enabled. -external floating : default is 0. 126 io vlan tag enable jumper setting function after power on reset. -external pull_high = 1, means mac receiving accept 1522 bytes packet (vlan tag enable). -external pull_low = 0, means mac receiving reject 1522 bytes packet (vlan tag disable). -external floating : default is 0. MTD502EF(128pqfp) jumper setting table after power on reset pin no. io setting function descriptions
11/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 3.0 mtd502eg (80lqfp) pin descriptions mtd502eg(80lqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions 1 o (nc) crs0 (nc) (nc) pin 77~80, 1~20 for port0, suitable for connecting with 10/100phy , risc_cpu, switch,.... 2 o txd0_1 rxd0_1 (nc) (nc) 3 o txd0_0 rxd0_0 (nc) (nc) 4 o txen0 rxdv0 (nc) (nc) 5 i txc0 (nc) (nc) (nc) 6 gnd 7 i rxc0 (nc) crsdv0 txen0 8 o (nc) rxc0 txd0_1 rxd0_1 9 o (nc) col0 txd0_0 rxd0_0 10 o (nc) txc0 txen0 crsdv0 11 i rxd0_0 txd0_0 rxd0_0 txd0_0 12 i rxd0_1 txd0_1 rxd0_1 txd0_1 13 i full0 full0 full0 (nc) 14 o (nc) (nc) (nc) (nc) 15 i rxd0_2 txd0_2 (nc) (nc) 16 i rxd0_3 txd0_3 (nc) (nc) 17 i rxdv0 txen0 (nc) (nc) 18 i crs0 speed0 speed0 (nc) 19 i col0 (nc) (nc) (nc) 20 i speed0 (nc) (nc) (nc) 21 i link1 (nc) (nc) (nc) pin 21~41 for port1, suitable for con- necting with homepna phy. 22 o txd1_3 (nc) (nc) (nc) 23 o txd1_2 (nc) (nc) (nc) 24 o (nc) (nc) (nc) (nc) 25 o txd1_1 (nc) (nc) (nc) 26 o txd1_0 (nc) (nc) (nc) 27 o txen1 (nc) (nc) (nc) 28 i txc1 (nc) (nc) (nc) 29 i rxc1 (nc) (nc) (nc) 30 i rxd1_0 (nc) (nc) (nc) 31 i rxd1_1 (nc) (nc) (nc) 32 i full1 (nc) (nc) (nc) 33 o (nc) (nc) (nc) (nc) 34 i rxd1_2 (nc) (nc) (nc) 35 i rxd1_3 (nc) (nc) (nc) 36 vcc 37 gnd 38 i rxdv1 (nc) (nc) (nc) 39 i crs1 (nc) (nc) (nc)
12/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 40 i col1 (nc) (nc) (nc) 41 vcc * 42 i speed1 (nc) (nc) (nc) 43 vcc 44 vcc 45 gnd 46 gnd 47 gnd 48 gnd 49 io co1_d co1_d co1_d co1_d port1: col led display, low_active. * when in half duplex mode: this led pin present port1?s collision event. 50 io co0_d co0_d co0_d co0_d port0: col led display, low_active. * when in half duplex mode: this led pin present port0?s collision event. 51 gnd 52 gnd 53 io fdco1_d fdco1_d fdco1_d fdco1_d port1: full/col led display, low_active. * when in full duplex mode: this led pin is always in low_active. when in half duplex mode: this led pin present port1?s collision event, using flash style for display. 54 io fdco0_d fdco0_d fdco0_d fdco0_d port0: full/col led display, low_active. * when in full duplex mode: this led pin is always in low_active. when in half duplex mode: this led pin present port0?s collision event, using flash style for display. 55 io lnac1_d lnac1_d lnac1_d lnac1_d port1: link_activity led display, low_active. * when in link_on state : this led pin is always in low_active. when have tx or rx activity in this port : this led pin present port1?s tx/rx activity, using flash style for display. mtd502eg(80lqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions
13/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology note: input signal link,speed,full from phy device are low_active definnition. 56 io lnac0_d lnac0_d lnac0_d lnac0_d port0: link_activity led display, low_active. * when in link_on state : this led pin is always in low_active. when have tx or rx activity in this port : this led pin present port0?s tx/rx activity, using flash style for display. 57 io lnrx1_d lnrx1_d lnrx1_d lnrx1_d port1: link_rx led display, low_active. * when in link_on state : this led pin is always in low_active. when have rx activity in this port : this led pin present port1?s rx activity, using flash style for display. 58 io lnrx0_d lnrx0_d lnrx0_d lnrx0_d port0: link_rx led display, low_active. * when in link_on state : this led pin is always in low_active. when have rx activity in this port : this led pin present port0?s rx activity, using flash style for display. 59-61 io (nc) (nc) (nc) (nc) 62 vcc 63 io (nc) (nc) (nc) (nc) 64 gnd 65-69 io (nc) (nc) (nc) (nc) 70 io (nc) p0mdio (nc) p0mdio 71 io (nc) p0mdc (nc) p0mdc 72 o clk25o clk25o clk25o clk25o clock 25mhz output. 73 vcc 74 i sysclk sysclk sysclk sysclk system clock input, 50mhz operation. 75 io (nc) (nc) (nc) (nc) 76 i rstb rstb rstb rstb system resetb input, low_active. 77 i link0 (nc) link0 (nc) 78 o txd0_3 rxd0_3 (nc) (nc) 79 vcc 80 o txd0_2 rxd0_2 (nc) (nc) mtd502eg(80lqfp) pin definition mapping under different configurations pin no. i/o mii mode phy_mii mode rmii mode phy_rm ii mode descriptions
14/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology mtd502eg(80lqfp) jumper setting table after power on reset pin no. io setting function descriptions 1 io 2p_sw enable jumper setting function after power on reset. -external pull_high = 1, means enter 2 port switch mode. -external pull_low = 0, means an internal test mode. -external floating : default is 0. for mtd502e application, this pin must always use ?external pull_hgih? for well operation. 10 io back pressure disable jumper setting function after power on reset. -external pull_high = 1, means back_pressure function ( under half_duplex) is disabled for two ports both. -external pull_low = 0, means back_pressure function enable. -external floating : default is 0. 57 io p0_rmii enable jumper setting function after power on reset. -external pull_high = 1, means port 0 rmii interface enable.. -external pull_low = 0, means port 0 is mii interface. -external floating : default is 0. 58 io p0_phy_mode enable jumper setting function after power on reset. -external pull_high = 1, means port 0 interrface enter phy mode. -external pull_low = 0, means port 0 interface is using mac mode. -external floating : default is 0. 59 io p1_bkoff_4 enable jumper setting function after power on reset. -external pull_high = 1, means port 1 mac backoff engine is using limit_4 modified method. -external pull_low = 0, means port 1 mac backoff engine is using specification defined method. -external floating : default is 0. 60 io p0_bkoff_4 enable jumper setting function after power on reset. -external pull_high = 1, means port 0 mac backoff engine is using limit_4 modified method. -external pull_low = 0, means port 0 mac backoff engine is using specification defined method. -external floating : default is 0. 61 io deviceid[4] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0.
15/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 63 io deviceid[3] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 65 io deviceid[2] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 66 io deviceid[1] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 67 io deviceid[0] jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0. 68 io p1_crcchk disable jumper setting function after power on reset. -external pull_high = 1, means port1 crc check and drop function is disabled. -external pull_low = 0, means port1 crc check and drop function is enabled. -external floating : default is 0. 69 io p0_crcchk disable jumper setting function after power on reset. -external pull_high = 1, means port0 crc check and drop function is disabled. -external pull_low = 0, means port0 crc check and drop function is enabled. -external floating : default is 0. 71 io vlan tag enable jumper setting function after power on reset. -external pull_high = 1, means mac receiving accept 1522 bytes packet (vlan tag enable). -external pull_low = 0, means mac receiving reject 1522 bytes packet (vlan tag disable). -external floating : default is 0. mtd502eg(80lqfp) jumper setting table after power on reset pin no. io setting function descriptions
16/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 4.0 functional descriptions the mtd502e implements a 10/100m two port switch for 10m/100m packet switching. total 2k address entrys are provided for packets? sa learning and da routing; and also provide automatic aging function ( aging time = 300secs). when using in two port bridge application, the input packets from port0 will be stored in an embedded memory buffers of mtd502e first, while packets is good for for- warding ( crc chech ok, 64bytes < length > 1518bytes, and not local packets ) , than forward this packet to port1. 4.1 learning and routing the mtd502e supports 2k mac entries for filtering. dynamic address learning is performed by each good unicast packet is completely received. the routing process is performed whenever the packet?s da is captured. if the da get a hit result in self port?s address table, this packet will be treated as a ? local packet?, and then drop the packet forwarding to the other port. on the other hand, if this packet is not a ?local packet?, then will be forwarded to the other port. 4.2 aging the address entries are scheduled in the aging machine. if one station does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time value is 300 seconds. 4.3 buffer queue management the buffer queue manager is implemented to manage the embedded memory packet buffering. the main function of the buffer queue manager is to maintain the linked list consists of buffer ids, which is used to show the corresponding memory address for each incoming packet. in addition, the buffer queue manager monitors the rested free spaces status of the memory buffers, if the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission id queue overflow happening. mtd502e provide back pressure control scheme in half duplex mode. 4.4 half duplex back pressure control in half duplex mode, mtd502e provide a back pressure control mechanism to avoid dropping packets during network conjection situation. when the ?back pressure control enable? bit is set during power on reset (pin_18 is external pull_low), it enables mtd502e supporting back pressure function in half_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value, mtd502e will send a jam pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid drop- ping packets. if the ?back pressure control disable? bit is set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. 4.5 mac and dma engine the mtd502e?s mac performs all the functions in ieee802.3 protocol, such as frame formatting, frame stripping, crc checking, bad packet dropping, defering to line traffic, and collision handling. the mac rx_engine checks incoming packets and drops the bad packet which include crc error, align- ment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the ?vlan tag 1522 bytes receive enable? bit is set during power on reset). before transmission, the mac tx_engine will constantly monitor the line traffic using derfering precedure. only if it has been idle for a 96 bits time (a minimum interpacket gap time, ipg time), actual transmmission can be started. for the half duplex mode, mac engine will detect collision; if a collision is detected, the mac tx_engine will transmit a jam pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (mtd502e implements the truncated exponential back_off algorithm defined in ieee 802.3 standard). for the full duplex mode, collision signal is ignored.
17/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 5.0 electrical characteristics 5.1 absolute maximum ratings 5.2 recommended operating conditions 5.3 dc electrical characteristics (under recommended operating conditions and vcc = 3.0 ~ 3.6v, tj = 0 to +115 o c) symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - vcc v t j commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-direction buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 0.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 2.4 v r i input pull-up/down resistance v il =0v or v ih =v cc 75 kohm
18/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 5.4 electrical characteristics symbol parameter min. typ. max. unit note t5 mii input setup time 10 ns t6 mii input hold time 10 ns t7 mii output setup time 3 ns t8 mii output hold time 5 ns symbol parameter min. typ. max. unit note t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns figure 1. mii timing rxclk0 crs0/rxdv0 txen0 txd0[3:0] rxd0[3:0] t5 t6 t7 t8 valid valid txclk0 figure 2. rmii timing refclk crsdv txen txd[1:0] rxd[1:0] t1 t2 t3 t4 valid valid
19/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 6.0 128 pin pqfp package data 103 128 1 38 39 64 65 102 seating plane see detail a a a 1 a 2 e b d 1 d e 1 e l l1 z detail a note: 1.dimension d1 & e1 do not include mold protrusion. but mold mismatch is included. allowable protrusion is .25mm/.010? per side. 2.dimension b does not include dambar protrusion. allowable dambar protru- sion .08mm/.003?. total in excess of the b dimemsion at maximum material condition. dambar cannot be located on the lower radius or the foot. 3.controlling dimension : millimeter. symbol dimension in inch dimension in mm min norm max min norm max a - - 0.134 - - 3.40 a1 0.010 - - 0.25 - - a2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.50 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 z 0 o - 7 o 0 o - 7 o y see detail b detail b c b with plating base metal gage plane
20/20 mtd502e revision 1.3 12/07/2000 mtd502e myson technology 7.0 80 pin lqfp package data 61 80 1 20 21 40 41 60 seating plane see detail a a a 1 a 2 e b d 1 d e 1 e l l1 detail a symbol dimension in inch dimension in mm min norm max min norm max a - - 0.063 - - 1.60 a1 0.002 - 0.006 0.05 - 0.15 a2 0.053 0.055 0.057 1.35 1.4 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 b 1 0.007 0.008 0.009 0.17 0.20 0.23 c 0.004 - 0.008 0.09 - 0.20 c 1 0.004 - 0.006 0.09 - 0.16 d 0.551 bsc 14.00 bsc d 1 0.472 bsc 12.00 bsc e 0.551 bsc 14.00 bsc e 1 0.472 bsc 12.00 bsc e 0.020 bsc 0.50 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref r 1 0.003 - - 0.08 - - r 2 0.003 - 0.008 0.08 - 0.2 see detail b detail b c b with plating base metal gage plane c 1 b 1 r 2 r 1

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